FIGS. 1-3 are sectionally perspective views, respectively illustrating a structure and a manufacturing method of a conventional static induction thyristor.
The conventional static induction thyristors of this type have been manufactured as follows:
First, as shown in FIG. 1, a P.sup.+ -type gate region 314 is selectively formed in a main surface of an N.sup.- -type substrate 310 by selectively diffusing P-type impurities into the main surface. Then, as shown in FIG. 2, on the N.sup.- -type substrate 310 is formed an N.sup.- -type epitaxial layer 320 by a chemical vapor deposition. At this time, the P.sup.+ -type gate region 314 is extended in this N.sup.- -type epitaxial layer 320 due to an automatic doping.
Next, as illustrated in FIG. 3, in the lower surface of the N.sup.- -type substrate 310 is formed a P.sup.+ -type layer 312 by an impurity diffusion, and in the upper surface of the N.sup.- -type epitaxial layer 320 is formed an N.sup.+ -type layer 322 also by the impurity diffusion. Then, an anode electrode 340 is formed on the lower surface of the P.sup.+ -type layer 312, and a cathode electrode 350 is formed on the upper surface of the N.sup.+ -type layer 322.
In the thus-obtained static induction thyristor 300, the P.sup.+ -type layer 312 functions as an anode region, N.sup.+ -type layer 322 as a cathode region, both of the N.sup.- -type substrate 310 and N.sup.- -type epitaxial layer 320 function as an N-type base 360, and the P.sup.+ -type gate region 314 functions as a gate which controls an anode current flowing between the anode electrode 340 and the cathode electrode 350.
FIGS. 4-6 are sectionally perspective views, respectively illustrating a structure and a manufacturing method of a conventional GTO thyristor.
The conventional GTO thyristors of this type have been manufactured in the following manner:
First, as shown in FIG. 4, a P-type layer 416 is formed in the upper surface of an N.sup.- -type substrate 410 by an impurity diffusion, and then, a P.sup.+ -type gate region 414 is selectively formed in a main surface of the P-type layer 416 by selectively diffusing P-type impurities into the main surface.
Next, as depicted in FIG. 5, a P-type epitaxial layer 420 is formed on the P-type layer 416 by a chemical vapor deposition. At this time, the P.sup.+ -type gate region 414 is expanded into this P-type epitaxial layer 420 due to an automatic doping.
Next, as shown in FIG. 6, a P-type layer 412 is formed in the lower surface of the N.sup.- -type substrate 410 by an impurity diffusion, and an N-type layer 422 is formed in the upper surface of the P-type epitaxial layer 420 by the impurity diffusion. Then, an anode electrode 440 is formed on the lower surface of the P-type layer 412, and a cathode electrode 450 is formed on the upper surface of the N-type layer 422.
In the thus-obtained GTO thyristor 400, the P-type layer 412 and N-type layer 422 function as P-type emitter and N-type emitter, respectively, the N.sup.- -type substrate 410 functions as an N-type base, the P-type layer 416 and the P-type epitaxial layer 420 function as P-type base 460, and the P.sup.+ -type gate region 414 functions as a gate which controls an anode current flowing between the anode electrode 440 and the cathode electrode 450.
FIGS. 7 and 8 are sectionally perspective views, respectively illustrating a structure and a manufacturing method of a conventional static induction thyristor with a gate metal.
The conventional static induction thyristor with a gate metal of this type have been manufactured as follows. First, as shown in FIG. 7, a groove 526 is formed in the upper surface of an N.sup.- -type substrate 510 by a wet or dry etching method. Then, an N.sup.+ -type layer 522 and P-type layer 512 are respectively formed in the upper and lower surfaces of the N.sup.- -type substrate 510 by an impurity diffusion, and further, a P.sup.+ -type gate region 514 is formed in the bottom surface of the groove 526.
Next, as seen in FIG. 8, there are formed a gate metal 530 on the P.sup.+ -type gate region 514, a cathode electrode 550 on the upper surface of the N.sup.+ -type layer 522, and an anode electrode 540 on the lower surface of the P-type layer 512.
In the thus-obtained static induction thyristor 500 with a gate metal, the P-type layer 512 and N.sup.+ -type layer 522 function as an anode region and a cathode region, respectively, the N.sup.- -type substrate 510 functions as an N-type base, and the P.sup.+ -type gate region 514 functions as a gate which controls an anodic current flowing between the anode electrode 540 and the cathode electrode 550.
FIGS. 9 and 10 are sectionally perspective views, respectively illustrating a structure and a manufacturing method of a conventional GTO thyristor with a gate metal.
The conventional GTO thyristor with a gate electrode of this type have been manufactured as follows:
First, as explained before with reference to FIGS. 4 and 5, a P-type layer 616 is formed on an N.sup.- -type substrate 610 by an epitaxial growth, which utilizes an impurity diffusion or chemical vapor deposition.
Then, as shown in FIG. 9, an N-type layer 622 and a P-type layer 612 are respectively formed in the upper surface of the P-type layer 616 and the lower surface of the N.sup.- -type substrate 610 by the impurity diffusion. Next, a groove 626 is formed in the P-type layer 616 by a wet or dry etching, and a P.sup.+ -type gate region 614 is formed in the bottom surface of this groove 626.
Then, as illustrated in FIG. 10, a gate metal 630 is formed on the P.sup.+ -type gate region 614, a cathode electrode 650 on the N-type layer 622, and an anode electrode 640 is formed on the P-type layer 612.
In the thus-obtained GTO thyristor 600 with a gate electrode, the P-type layer 612 functions as a P-type emitter, the N-type layer 622 as an N-type emitter, the N.sup.- -type substrate 610 as an N-type base, the P-type layer 616 as a P-type base, and the P.sup.+ -type gate region 614 functions as a gate which controls an anodic current flowing between the anode electrode 640 and the cathode electrode 650.
In the conventional static induction thyristor 300 shown in FIG. 3, the P.sup.+ -type gate region 314 doped with impurities at a high concentration is buried in the N-type base 360 for the purpose of increasing a maximum cutoff current. In order to bury the P.sup.+ -type gate region 314 within the N-type base 360, it is required that the P.sup.+ -type gate region 314 is selectively formed in a main surface of the N.sup.- -type substrate 310 as shown in FIG. 1, and then the N.sup.- -type epitaxial layer 320 is formed on the N.sup.- -type substrate 310 by a chemical vapor deposition.
Since the N.sup.- -type epitaxial layer 320 is formed on the N.sup.- -type substrate 310, in which the P.sup.+ -type gate region 314 has already been selectively formed, crystal defects such as stacking fault are liable to be produced in the N.sup.- -type epitaxial layer 320, especially in the portions grown on the P.sup.+ -type gate region 314. Also, since the property of the crystals on the P.sup.+ -type gate region 314 is different from that of the crystals on the N.sup.- -type substrate 310, there cannot be obtained a uniform N.sup.- -type epitaxial layer 320 of good quality. Consequently, there cannot be obtained a uniform N-type base 360 of good quality.
Furthermore, since this epitaxial growth is conducted at about 1100.degree. C. under an atmospheric pressure, impurities in the P.sup.+ -type gate region 314 are diffused into the N.sup.- -type substrate 310 and the N.sup.- -type epitaxial layer 320 during the epitaxial growth. In some cases, the conductivity type of the N.sup.- -type substrate 310 as well as that of the N.sup.- -type epitaxial layer 320 are changed from N-type to P-type in the portions lying between the P.sup.+ -type gate regions 314, so that it is no longer possible to control the anode current by means of the P.sup.+ -type gate regions 314.
In addition, since the impurities in the P.sup.+ -type gate region 314 give bad influences on the crystallinity of the N.sup.- -type epitaxial layer 320 and the anode current, there is an upper limit for the impurity concentration in the P.sup.+ -type gate region 314. As a result, the maximum cutoff current cannot be increased beyond a certain upper limit.
In the conventional GTO thyristor 400 shown in FIG. 6, the P.sup.+ -type gate region 414 having impurities doped at a high concentration is buried in the P-type base 460 for the purpose of increasing a maximum cutoff current. In order to bury the P.sup.+ -type gate region 414 within the P-type base 460, it is required that the P.sup.+ -type gate region 414 is selectively formed in a main surface of the P-type layer 416 as shown in FIG. 4, and then the P-type epitaxial layer 420 is formed on the P-type layer 416 by a chemical vapor deposition.
Since the P-type epitaxial layer 420 is formed on the P-type layer 416, in which the P.sup.+ -type gate region 414 has already been selectively formed, crystal defects such as stacking fault are likely to come about in the P-type epitaxial layer 420, especially in the portions grown on the P.sup.+ -type gate region 414. Also, since the property of the crystals on the P.sup.+ -type gate region 414 is different from that of the crystals on the P-type layer 416, there cannot be obtained a uniform P-type epitaxial layer 420 of good quality. Consequently, there cannot be obtained a uniform P-type base 460 of good quality.
Moreover, since the impurities in the P.sup.+ -type gate region 414 affect the crystallinity of the P-type epitaxial layer 420, there is an upper limit for the impurity concentration in the P.sup.+ -type gate region 414. As a result, the maximum cutoff current cannot be increased beyond a certain upper limit.
In the conventional static induction thyristor with a gate electrode shown in FIG. 8, the gate metal 530 is provided on the P.sup.+ -type gate region 514, so that a gate lateral resistance is reduced, thereby increasing the maximum cutoff current. However, since it is necessary to form the groove 526, which penetrates the N.sup.+ -type layer 522 to reach the P.sup.+ -type gate region 514, there is a problem that N.sup.+ -type layer 522 which functions as the cathode region is divided into small pieces, thereby increasing the resistance.
In this connection, it is preferable to use a dry etching method for forming the groove 526, because it causes less under etching. However, since the dry etching is low in etching rate, there arises another problem that it requires a quite long time to form such a deep groove as the groove 526, which reaches the P.sup.+ -type gate region 514 through the N.sup.+ -type layer 522.
It is also difficult to provide the gate metal 530 on the P.sup.+ -type gate region 514, which is exposed in the bottom area of the groove 526 having such a large aspect ratio.
In the conventional GTO thyristor with a gate electrode shown in FIG. 10, the gate metal 630 is also formed on the P.sup.+ -type gate region 614, so that a gate lateral resistance is reduced, thereby increasing the maximum cutoff current. However, since it is necessary to form the groove 626, which penetrates the N-type layer 622 to reach the P.sup.+ -type gate region 614, there is a problem that N-type layer 622 which functions as the N-type emitter is divided into small pieces, thereby increasing the resistance.
It is preferable to use a dry etching method for forming the groove 626, because it causes less under etching. However, since the dry etching has a low etching rate, there is such a problem that it requires a long time to form such a deep groove as the groove 626, which penetrates the N-type layer 622 to reach the P.sup.+ -type gate region 614.
In addition, it is also difficult to provide the gate metal 630 on the P.sup.+ -type gate region 614, which is exposed in the bottom area of the groove 626 having such a large aspect ratio.
Accordingly, an object of the present invention is to mitigate the problems inherent in the conventional semiconductor devices and to provide a semiconductor device having a large maximum cutoff current, a low gate resistance and stable properties.
It is another object of the present invention to provide a method of manufacturing such a semiconductor device reliably with high throughput.